Frequency Timing Generator (FTG) integrated circuit (IC) devices, e.g., “chips,” are widely used in the electronics industry. A conventional phase lock loop (PLL) frequency timing generator device is shown in FIG. 1. The frequency timing generator device of FIG. 1 comprises a comparator and up/down counter feeding an M-counter and an N-counter. The M-counter and N-counter is coupled to the input of a phase/frequency divider, which is coupled to the input of a charge pump, which is coupled to the input of a loop filter, which is coupled to the input of a voltage controlled oscillator (VCO). The output of the VCO is fed back to the input of the N-counter, forming a feedback loop. A reference frequency Fref is coupled to the input of the M-counter.
In FTG devices, different frequency output selections may be chosen, and are usually listed in a frequency table. A default frequency selection table is typically supplied with most FTG devices, but many users prefer to generate their own frequency outputs by programming M and N dividers in the PLL. This is sometimes referred to as dial-a-frequency (DAF) feature. A new frequency may be programmed either through selection from frequency table (e.g., with hardware) or with a System Management Bus (SMBUS). SMBUS effectively comprises a serial data interface, similar in some respects to I1C compliant interfaces.
To enhance the flexibility and function of the clock synthesizer, a two wire serial interface is provided in the FTGs. Through this interface, various device functions can be programmed. Such functions can include frequency selection using, e.g., the FTG frequency table or DAF. Once a new frequency is programmed, the output frequency transitions its behavior from the original frequency to the target frequency. This transition is called frequency switching. Typically, smoothness is a desirable attribute of frequency switching.
A conventional frequency smooth switching algorithm relies on detecting the new values of dividers (e.g., higher-lower-equal) via a comparator and step-by-step increments or decrements of M (reference divider) and N (feedback divider) counters until target M and N values are reached. The slew rate of each step depends on the loop bandwidth for the N value of that step. In order to support all frequency selections of the FTG, the VCO of the PLL should work at its linear region for a maximum and minimum frequencies without stability related issues. This typically requires a VCO with a gain value KVCO, which is stated in units of Megahertz per Volt (MHz/V), and a charge pump (ICP) current with a loop filter configuration (resistor R1, capacitor C1, capacitor C2 as shown in the FIG. 2).
As the frequency range of the PLL increases, the bandwidth (proportional to KVCO, ICP and R1 of the loop filter) increases. This increase in bandwidth also increases the frequency transition slew rate that should be limited for FTGs, which allows systems using the FTGs to correctly follow the output frequency. Some modern FTG circuits are designed to achieve a maximum slew rate that is less than 300 kHz per microsecond (300 KHz/μs). However, control of the slew rate during transition can be difficult for conventional solutions to achieve. Further, the transitions characterizing conventional solutions is substantially non-linear.
DAF features typically rely on programming both M and N dividers, which can be programmed simultaneously or one at a time, depending on the target frequency. The VCO output frequency equals the reference frequency multiplied by the value of N divided by M. The target frequency is directly proportional to the N divider value, and inversely proportional to the M-divider value.
Conventional circuits change one divider at a time and conventional switching methods give priority to decreasing frequency outputs. Thus conventionally, when both the M-divider and N-divider values are programmed, priority is given to either the M or N divider depending on which one decreases the frequency first. The remaining divider is modified later to further decrease or increase the frequency depending on programmed value.
In the situation where both dividers are modified for a higher frequency, there may arise a situation, for example, where the original M and N values are (M, N)=(39, 208), resulting in the Fvco=800 Mhz (Fref=150 MHz). Where the target M and N values are (M, N)=(42, 226) the resulting Fvco=807 Mhz. In the conventional circuit, this selection causes the M divider to change first from 39 to 42 (step-by-step) decreasing Fvco=742 Mhz and then N changes one by one from 208 to 226 and the target frequency is reached (807 Mhz). Even though the difference between the target and the original frequency is close (7 Mhz only) the conventional method requires a dip of 65 Mhz first followed by an 84 Mhz increase. This can be inefficient and can increase the transition time and the power required.
Conventional switching solutions attempt to smooth a switching block using a ‘step’ approach. The total frequency switch from the starting frequency to the final frequency comprises frequency steps where the M or N value was increased or decreased by one at each increment as appropriate to reach the target frequency. In the conventional solution when the values of the M divider and N divider are both changed together, one is changed before the other. This can result in unnecessary frequency dips when both the M divider and N divider are changed by large amounts even though frequency stayed close to the starting point.
Thus, conventional solutions demand that new M and N values be changed one by one and must approach their target values in a step-by-step manner. This can increase the time it takes to reach the target frequency. Further, in conventional solutions the slew rate is controlled by the bandwidth (BW) of the PLL and may be too high (e.g., out of specifications) for high frequency PLLs, such as those used in some more modern FTG applications. Moreover, resources such as the number of gates and/or die area required to perform the step-by-step conventional behavior tend to be costly, time required for simulation and verification can be significant, and thus conventional solutions can be expensive in several ways.